References to Advisories, Solutions, and Tools

By selecting these links, you will be leaving NIST webspace. We have provided these links to other web sites because they may have information that would be of interest to you. No inferences should be drawn on account of other sites being referenced, or not, from this page. There may be other web sites that are more appropriate for your purpose. NIST does not necessarily endorse the views expressed, or concur with the facts presented on these sites. Further, NIST does not endorse any commercial products that may be mentioned on these sites. Please address comments about this page to nvd@nist.gov.

Change History

In the Linux kernel, the following vulnerability has been resolved:

spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer

While transmitting with rx_len == 0, the RX FIFO is not going to be
emptied in the interrupt handler. A subsequent transfer could then
read crap from the previous transfer out of the RX FIFO into the
start RX buffer. The core provides a register that will empty the RX and
TX FIFOs, so do that before each transfer.

kernel.org https://git.kernel.org/stable/c/3feda3677e8bbe833c3a62a4091377a08f015b80 [No types assigned]

kernel.org https://git.kernel.org/stable/c/45e03d35229b680b79dfea1103a1f2f07d0b5d75 [No types assigned]

kernel.org https://git.kernel.org/stable/c/9cf71eb0faef4bff01df4264841b8465382d7927 [No types assigned]