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Change History

NEMU (OpenXiangShan/NEMU) before v2025.12.r2 contains an improper instruction-validation flaw in its RISC-V Vector (RVV) decoder. The decoder does not correctly validate the funct3 field when decoding vsetvli/vsetivli/vsetvl, allowing certain invalid OP-V instruction encodings to be misinterpreted and executed as vset* configuration instructions rather than raising an illegal-instruction exception. This can be exploited by providing crafted RISC-V binaries to cause incorrect trap behavior, architectural state corruption/divergence, and potential denial of service in systems that rely on NEMU for correct execution or sandboxing.

https://docs.riscv.org/reference/isa/unpriv/v-st-ext.html

https://github.com/OpenXiangShan/NEMU/commit/481de637d5fc5838356caee80a79e56a33754039

https://github.com/OpenXiangShan/NEMU/issues/952

https://github.com/OpenXiangShan/NEMU/pull/958