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CVE-2026-29644 Detail

Description

XiangShan (open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) has improper gating of its distributed CSR write-enable path, allowing illegal CSR write attempts to alter custom PMA (Physical Memory Attribute) CSR state. Though the RISC-V privileged specification requires an illegal-instruction exception for non-existent/illegal CSR accesses, affected XiangShan versions may still propagate such writes to replicated PMA configuration state. Local attackers able to execute code on the core (privilege context depends on system integration) can exploit this to tamper with memory-attribute enforcement, potentially leading to privilege escalation, information disclosure, or denial of service depending on how PMA enforces platform security and isolation boundaries.


Metrics

NVD enrichment efforts reference publicly available information to associate vector strings. CVSS information contributed by other sources is also displayed.
CVSS 4.0 Severity and Vector Strings:

NIST CVSS score
NIST: NVD
N/A
NVD assessment not yet provided.

References to Advisories, Solutions, and Tools

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URL Source(s) Tag(s)
https://docs.riscv.org/reference/isa/priv/priv-csrs.html MITRE
https://github.com/OpenXiangShan/XiangShan/commit/2b1f9796aa98597e5eeac32e5bb1418496987ca4 MITRE
https://github.com/OpenXiangShan/XiangShan/commit/edb1dfaf7d290ae99724594507dc46c2c2125384 MITRE
https://github.com/OpenXiangShan/XiangShan/issues/3959 CISA-ADP, MITRE
https://xiangshan-doc-test.readthedocs.io/next/memory/mmu/pmp_pma/ MITRE

Weakness Enumeration

CWE-ID CWE Name Source
CWE-284 Improper Access Control CISA-ADP  

Change History

2 change records found show changes

Quick Info

CVE Dictionary Entry:
CVE-2026-29644
NVD Published Date:
04/21/2026
NVD Last Modified:
04/21/2026
Source:
MITRE